A. Field of the Invention
The present invention generally relates to integrated circuits. In particular, it relates to forming a diffusion barrier layer comprising a polyelectrolyte monolayer, bilayer, or multilayers in order to prevent diffusion of a metal interconnect (e.g. copper) into a semiconductor or insulating material (e.g. Si or SiO2).
B. Description of Related Art
In order to achieve the increasing demands for semiconductor performance, many new manufacturing techniques are being developed and introduced. Increasing demands are resulting in shrinking dimensions in order to accommodate more circuits on a chip, and increasing operating speeds, which approach the inherent delay in traditional semiconductor materials.
Copper is the preferred metal for creating multilevel interconnect structures in ultra-large-scale-integrated (ULSI) circuits because of its high electrical conductivity and electromigration resistance [Ref. 1]. As a conductor, Cu has a lower resistivity and higher electromigration resistance than traditional Al—Si—Cu alloy and can also reduce costs because smaller lines can be used to carry the same amount of current. As a result, tighter packing density can be achieved on a given semiconductor level. Furthermore, the use of many low dielectric-constant materials such as fluorinated SiOx is critical for achieving greater device speeds. (W. Chang, S. M. Jang, C. H. Yu, S. C. Sun, and M. S. Liang, San Francisco, Calif., USA, 1999 (IEEE, Piscataway, N.J.), p. 295, 131–3; G. S. Chen and S. T. Chen, J. Appl. Phys. 87, 8473 (2000).) It is thus crucial to devise solutions to prevent Cu diffusion across SiOx-based materials.
The traditional dielectric, silicon dioxide (k=3.9), can be replaced by low k materials (k of about 1.2 to 3.0). The integration of copper with porous ultralow k interlayer dielectrics has attracted significant interest because the combination will lead to additional performance improvements in reducing the resistance-capacitance (RC) time delay of integrated circuits. However, copper diffuses rapidly in silicon, silicon dioxide and other low k materials. Many low-k materials have been proposed for use in semiconductor devices, such as fluorine-doped Sio2, methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), parylene, and benzocyclobutene polymers. The diffusion, over time, through the dielectric material, results in junction linkage, which decreases device efficiency.
One of the challenges in Cu metallization technology is to prevent the rapid diffusion of Cu into SiO2 under an electrical bias during device operation. This is because Cu incorporation degrades the dielectric properties of the oxide layer, causing leakage currents and leading to inferior device performance and failure. (J. D. McBrayer, R. M. Swanson, and T. W. Sigmon, J. Electrochecm. Soc. 133, 1243 (1986).)
To address the problem of copper diffusion, researchers have developed “diffusion barriers.” A diffusion barrier is part of the metallization scheme, comprising a layer of material formed between an overlying copper layer and an underlying silicon or silicon dioxide layer. The diffusion barrier serves to inhibit the diffusion of copper into the surrounding layer. The problems associated with ultrathin (1–10 nm) diffusion barriers are disclosed in Sun et al., “How Pore Size and Surface Roughness Affect Diffusion Barrier Continuity on Porous Low-k Films,” J. Electrochemical Society 150(5)F97-F101 (2003). The diffusion barrier studied was tantalum (Ta). Ta has many good properties as a diffusion barrier because it has a high melting point and therefore a high activation energy for diffusion.
Several researchers have advocated the use of congruent 10 to 30-nm-thick diffusion barrier layers of Ti- or Ta-based compounds or Cu-based alloys to alleviate this problem. (C. Ahrens, D. Depta, F. Schitthelm, and S. Wilhelm, Appl. Surf. Sci. 91, 285–90 (1995); P. J. Ding, W. A. Lanford, S. Hymes, and S. P. Murarka, Appl. Phys. Lett. 64, 2897 (1994); and, P. J. Ding, W. A. Lanford, S. Hymes, and S. P. Murarka, Appl. Phys. 75, 3627 (1994).) While this approach has been successful thus far, new types of barriers are likely to be needed at device dimensions below 100 nm in contemporary device architectures, and very high-aspect ratio structures in 3D-integration of multiple-wafer devices. The barrier layer thickness should be kept below 5 nm for future devices to fully realize the advantage of high conductivity Cu. This is difficult to achieve by conventional physical and chemical vapor deposition methods without compromising either conformal coverage of high aspect ratio features and/or the barrier layer microstructure, both of which reduce the efficacy of the barrier. (A. Z. Moshfegh and O. Akhavan, Thin Solid Films 370, 10 (2000); A. Sekiguchi, J. Koike, and K. Maruyama, J. Japan Inst. Metals 64, 379 (2000).)
The use of amorphous alloys as diffusion layers has been discussed. Amorphous binary silicides, such as molybdenum-, tantalum and tungsten silicide and amorphous ternary alloys (e.g., Ti—Si—N) have been reported as diffusion barriers. The formation of these layers, however, uses sophisticated sputtering processes and results in the inclusion of substantial contaminants.
Diffusion barriers made of TiN, TiSiN and TiN/TiSiN have also been reported. The titanium was deposited by sputtering in the presence of ammonia, which was used as a nitridation agent. A two-step annealing process completed the layer formation. Currently used interfacial barrier layers based on transition metals or their compounds [Ref. 2], formed by conventional vapor deposition methods, do not form uniform and continuous films at thicknesses below 10 nm, especially in non-planar topographies with high (e.g., 5:1) depth-to-width aspect ratios. Such high barrier layer thicknesses of these high-resistivity materials take up the space meant for low-resistivity Cu, thereby neutralizing the advantages of Cu metallization in sub-100-nm devices. Furthermore, even if <5-nm-thick conformal films are achieved, it is not clear if conventional barrier materials will be effective at these thicknesses due to fast diffusion paths such as nanopipes [Ref. 3], or grain boundary generation due to phase formation or compositional changes caused by interfacial intermixing.
While a number of diffusion barriers have been discussed in the art, improved diffusion barriers are always desirable, especially diffusion barriers that are formed in very thin (nanometer-scale) layers.
The shrinking dimensions of semiconductor circuits also causes a high aspect ratio (i.e. small feature size and deep trenching) in the surface topology of the chip. This means that a diffusion barrier that is used must have good continuity and conformality in order to act as a viable diffusion barrier. In addition, the barriers must be very thin in order to maintain the advantage of low effective resistance or capacitance achieved through combination of Cu and low-k materials.
Researchers including the present inventors have recently demonstrated [Refs. 4,5] the use of sub-5-nm self-assembled layers of short (few nm) amphiphilic organosilane molecules as diffusion barriers. The underlying rationale of this work was to immobilize Cu through strong local interfacial bonding with short-chained molecular moieties that are organized on the substrate in an ordered fashion, and create a vacuum-like potential barrier between the Cu and the dielectric to prevent Cu ionization and transport. These molecules are anchored to substrate (and/or the overlayer) typically only at one point. The work referred to above as involving (in one embodiment) amphiphilic organosilanes was described in Ramanath et al. US PGPUB 2002/0105081 A1.
The present invention comprises the use of layers of oligomers and polymers (long-chained molecules) with multiple points at which the layer is electrostatically or covalently anchored to the underlayer and/or the overlayer. While such layers are typically disordered, ordered configurations are also conceivable. As described below, one embodiment of the invention involves the use of 3 to 5-nm-thick polyelectrolyte bilayers and multilayers to inhibit Cu diffusion across dielectrics. It is well known that polyelectrolytes can immobilize metal-ions through electrostatic, covalent or coordinate-covalent bonding interactions, which can be tuned by appropriate choice of functional groups [Refs. 6,7,8,9,10,11,12]. As described herein, alternating electrostatic adsorption of polycations and polyanions is a convenient, versatile technique for forming ultrathin films, and allows the exploration of multilayers as barriers [Refs. 13, 14]. Furthermore, the use of polymeric structures as barriers could open up possibilities of integrating them, or their constituents, with low-k dielectric materials or their precursors, thereby obviating the need for barriers for Cu/low-k metallization technology.